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d a t a sh eet objective speci?cation supersedes data of 1995 dec 08 file under integrated circuits, ic01 1996 jul 17 integrated circuits TDA1388 bitstream continuous calibration filter-dac for cd-rom audio applications
1996 jul 17 2 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 features multiple format input interface i 2 s-bus and lsb-justified input format compatible 1f s input format data rate. extensive channel manipulation features separate soft mute on left and right channel channel interchange function (left to right and right to left) monaural function (left to right or right to left) true mono function 1 2 (left plus right). digital sound processing separate digital volume control for left and right channels digital tone control, bass boost and treble db-linear volume and tone control (low microcontroller load) digital de-emphasis soft mute. advanced audio output con?guration stereo line output (under microcontroller volume control) stereo headphone output (under 5-tap potentiometer volume control) line output independent of headphone output volume power on/off click prevention circuitry high linearity, dynamic range, low distortion. general integrated digital filter plus dac plus headphone driver no analog post filter required easy application functions controllable by static pins or by microcontroller interface 5 v power supply low power consumption small package size (so28 and ssop28). general description the TDA1388 cmos digital-to-analog bitstream converter incorporates an up-sampling digital filter and noise shaper, unique signal processing features and integrated line and headphone drivers. the digital processing features are of high sound quality due to the wide dynamic range of the bitstream conversion technique. the TDA1388 supports the i 2 s-bus data input mode with word lengths of up to 20 bits and the lsb justified serial data input format with word lengths of 16, 18 and 20 bits. two cascaded half-band filters and a sample-and-hold function increase the oversampling rate from 1f s to 64f s . a 2nd-order noise shaper converts this oversampled data to a bitstream for the 5-bit continuous calibration digital-to-analog converters (dacs). on board amplifiers convert the output current to a voltage signal capable of driving a line output. the signal is also used to feed the integrated headphone amplifiers. the volume of the headphone is controlled by an external potentiometer. the TDA1388 has special sound processing features for use in cd-rom audio applications, which can be controlled by static pins or microcontroller interface. these functions are de-emphasis, volume, bass boost, treble, soft mute and the channel manipulation functions needed for atapi-compliant functionality in cd-rom audio processing.
1996 jul 17 3 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 ordering information quick reference data notes 1. all v dd and v ss pins must be connected to the same supply or ground respectively. 2. measured at input code 00000h and v dd =5v. type number package name description version TDA1388t so28 plastic small outline package; 28 leads; body width 7.5 mm. sot136-1 TDA1388m ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm. sot341-1 symbol parameter conditions min. typ. max. unit supply v dd supply voltage note 1 4.5 5.0 5.5 v i dd supply current note 2 - 22 - ma v fs(rms) full-scale output voltage (rms value) v dd = 5 v 0.9 1.0 1.1 v (thd+n)/s total harmonic distortion plus noise as a function of signal for the line output 0 db signal; r l =5k w -- 85 - 80 db - 0.006 0.013 % - 60 db signal; r l =5k w -- 35 - 30 dba - 1.8 3.2 % total harmonic distortion plus noise as a function of signal for the headphone output 0 db signal; r l =16 w -- 65 - db - 0.056 - % 0 db signal; r l =32 w -- 70 - db - 0.032 - % - 60 db signal; r l =16 w or r l =32 w -- 35 - 30 dba - 1.8 3.2 % s/n signal-to-noise ratio a-weighted; at code 00000h 90 95 - dba br input bit rate at data input f sys = 256f s - 64f s - bits f sys = 384f s - 48f s - bits f sys system clock frequency 8.192 - 18.432 mhz t amb operating ambient temperature - 20 - +70 c
1996 jul 17 4 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 block diagram fig.1 block diagram. + - v dda v ssd v ddd tc 20 12 13 v ddo 28 v sso1 v sso2 1 21 v dda 22 v ssa 23 appl1 17 appl2 18 acp ws 19 10 bck 9 data 11 if2 8 if1 7 15 14 appl0 16 4f s 64f s 5 4 6 3 30 k w 30 k w 30 k w 30 k w 2 v ol v ref filtcl r conv1 r conv2 hpinl hpoutl TDA1388 27 hpoutr 25 v or 24 filtcr mgd015 + - 26 hpinr + - + - 16 (4-bit) calibrated current sources 16 (4-bit) calibrated current sinks left output switches 16 (4-bit) calibrated current sources 16 (4-bit) calibrated current sinks right output switches 2nd-order noise shaper data encoder sample-and-hold 16 oversampling filter stage 1 + 2 soft mute bass boost and treble volume control de-emphasis channel interchange serial data input 2nd-order noise shaper data encoder reference source reference source feature control unit timing sysclk syssel
1996 jul 17 5 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 pinning symbol pin description v sso1 1 operational ampli?er ground 1 hpoutl 2 left headphone output voltage hpinl 3 left headphone input voltage v ol 4 left channel audio voltage output filtcl 5 capacitor for left channel 1st-order ?lter function, should be connected between this pin and v ol (pin 4) v ref 6 internal reference voltage if1 7 input format selection 1 if2 8 input format selection 2 bck 9 bit clock input ws 10 word selection input data 11 data input v ddd 12 digital supply voltage v ssd 13 digital ground sysclk 14 system clock 256f s or 384f s syssel 15 system clock selection appl0 16 application mode 0 input appl1 17 application mode 1 input appl2 18 application mode 2 input acp 19 application control input tc 20 test control v sso2 21 operational ampli?er ground 2 v dda 22 analog supply voltage v ssa 23 analog ground filtcr 24 capacitor for right channel 1st-order ?lter function, should be connected between this pin and v or (pin 25) v or 25 right channel audio voltage output hpinr 26 right headphone input voltage hpoutr 27 right headphone output voltage v ddo 28 operational ampli?er supply voltage fig.2 pin configuration. handbook, halfpage TDA1388 mgd014 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v sso1 v sso2 v ref hpoutl hpinl v ol filtcl if1 if2 bck ws data v ddd v ssd sysclk v ddo hpoutr hpinr v or filtcr v ssa v dda tc acp appl2 appl1 appl0 syssel 28 27 26 25 24 23 22 21 20 19 18 17 16 15
1996 jul 17 6 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 functional description the TDA1388 cmos dac incorporates an up-sampling digital filter, a sample-and-hold register, a noise shaper, continuously calibrated current sources, line amplifiers and headphone amplifiers. the 1f s input data is increased to an oversampled rate of 64f s . this high-rate oversampling, together with the 5-bit dac, enables the filtering required for waveform smoothing and out-of-band noise reduction to be achieved by simple 1st-order analog post-filtering. system clock the TDA1388 accommodates slave mode only, this means that in all applications the system devices must provide the system clock. the system frequency is selectable. the options are 256f s and 384f s . the system clock must be locked in frequency to the i 2 s-bus input signals. table 1 system clock selection multiple format input interface the TDA1388 supports the following data input formats; i 2 s-bus with data word length of up to 20 bits. lsb justified serial format with data word length of 16, 18 or 20 bits. syssel description 0 256f s 1 384f s table 2 data input formats the input formats are illustrated in fig.3. left and right data-channel words are time multiplexed. input mode the TDA1388 has two input modes, a static-pin mode and a microcontroller mode. in the static-pin mode, the digital sound processing features such as mute left, mute right and de-emphasis are controlled by external pins. the other digital sound processing features have a default value. in the microcontroller mode, all the digital sound processing features can be controlled by the microcontroller. the controllable features are: de-emphasis volume left channel volume right channel flat/min/max switch bass boost treble channel manipulation modes. the selection of one of the two modes is controlled by the acp pin. when this pin is at logic 0 then the static pin mode will be selected. when the pin is at logic 1 then the microcontroller mode will be selected. if1 if2 format 00i 2 s-bus 0 1 lsb-justi?ed, 16 bits 1 0 lsb-justi?ed, 18 bits 1 1 lsb-justi?ed, 20 bits table 3 selectable values of the digital sound processing features features static-pin mode microcontroller mode de-emphasis 0 hz or 44.1 khz 0 hz or 44.1 khz volume left channel 0 db (?xed) 0 db to - db volume right channel 0 db (?xed) 0 db to - db flat/min/max switch ?at (?xed) ?at/min/max bass boost ?at set (?xed) ?at, min or max set treble ?at set (?xed) ?at, min or max set mute left channel external pin selectable (see table 4) mute right channel external pin selectable (see table 4) channel manipulation modes l_channel = l (?xed) selectable (see table 10) r_channel = r (?xed)
1996 jul 17 7 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 s tatic - pin mode in the static-pin mode most of the features have a default value (see table 3). the features that are controlled by the external pins are, mute left channel, mute right channel and de-emphasis. table 4 external pin feature control in the static-pin mode m icrocontroller mode the exchange of data and control information between the microcontroller and the TDA1388 is accomplished through a serial hardware interface comprising the following pins: appl0: microcontroller interface data line. appl1: microcontroller interface mode line. appl2: microcontroller interface clock line. information transfer through the microcontroller bus is organized in accordance with the so-called l3 format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see figs 4 and 5). the address mode is required to select a device communicating via the l3-bus and to define the destination registers for the data transfer mode. data transfer for the TDA1388 can only be in one direction, input to the TDA1388 to program its sound processing and other functional features. address mode the address mode is used to select a device for subsequent data transfer and to define the destination registers. the address mode is characterized by appl1 being low and a burst of 8 pulses on appl2, accompanied by 8 data bits. the fundamental timing is shown in fig.4. data bits 0 to 1 indicate the type of the subsequent data transfer as shown in table 5. pin feature appl0 mute left channel appl1 mute right channel appl2 de-emphasis table 5 selection of data transfer data bits 7 to 2 represent a 6-bit device address, with bit 7 being the msb and bit 2 the lsb. the address of the TDA1388 is 000101 (bit 7 to bit 2). in the event that the TDA1388 receives a different address, it will deselect its microcontroller interface logic. data transfer mode the selection preformed in the address mode remains active during subsequent data transfers, until the TDA1388 receives a new address command. the fundamental timing of data transfers is essentially the same as in the address mode, shown in fig.4. the maximum input clock and data rate is 64f s . all transfers are bitwise, i.e. they are based on groups of 8 bits. data will be stored in the TDA1388 after the eighth bit of a byte has been received. a multibyte transfer is illustrated in fig.6. programming the sound processing and other features the sound processing and other feature values are stored in independent registers. the first selection of the registers is achieved by the choice of data type that is transferred. this is performed in the address mode, bit 1 and bit 0 (see table 5). the second selection is performed by the 2 msbs of the data byte (bit 7 and bit 6). the other bits in the data byte (bit 5 to bit 0) is the value that is placed in the selected registers. when the data transfer of type data is selected, the features volume_r, volume_l, bass boost and treble can be controlled. when the data transfer of type status is selected, the features mode, de-emphasis, channel_manip_r and channel_manip_l can be controlled. bit 1 bit 0 transfer 0 0 data (volume left, volume right, bass boost and treble) 0 1 not used 1 0 status (de-emphasis, mode and channel-manipulation) 1 1 not used table 6 data transfer of type status bit 7 bit6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register selected 0 m1 m0 de or1 or0 ol1 ol0 mode (1 : 0), deemphasis, channel_ma- nip_r (1 : 0), channel_manip_l (1 : 0)
1996 jul 17 8 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 table 7 data transfer of type data note 1. x = dont care. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register selected 0 0 vr5 vr4 vr3 vr2 vr1 vr0 volume_r (5 : 0) 0 1 vl5 vl4 vl3 vl2 vl1 vl0 volume_l (5 : 0) 10x (1) bb4 bb3 bb2 bb1 bb0 bass boost (4 : 0) 11x (1) tr4 tr3 tr2 tr1 tr0 treble (4 : 0) mode: a 2-bit value to program the mode of the sound processing filters of bass boost and treble. there are three modes: flat, min and max. table 8 the ?at/min/max switch mode 1 mode 0 function 0 0 ?at 0 1 min 1 0 min 1 1 max de-emphasis: a 1-bit value to enable the digital de-emphasis filter. table 9 de-emphasis deem function 0 no de-emphasis 1 de-emphasis, 44.1 khz channel_manip_r and channel_manip_l: both are a 2 bit value to program the right or left channel manipulation. table 10 channel manipulation modes channel_manip_l<1 : 0> channel_manip_r<1 : 0> l_channel r_channel 00 00 mute mute 00 01 mute r 00 10 mute l 00 11 mute 1 2 (l+r) 01 00 r mute 01 01 r r 01 10 r l 01 11 r 1 2 (l+r) 10 00 l mute 10 01 l r 10 10 l l 10 11 l 1 2 (l+r) 11 00 1 2 (l + r) mute 11 01 1 2 (l + r) r 11 10 1 2 (l + r) l 11 11 1 2 (l + r) 1 2 (l+r)
1996 jul 17 9 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 volume_r: a 6-bit value to program the right channel volume attenuation (vr5 to vr0). the range is 0 db to - db in steps of 1 db. table 11 volume right settings volume_l: a 6-bit value to program the left channel volume attenuation (vl5 to vl0). the range is 0 db to - db in steps of 1 db. table 12 volume left settings vr5 vr4 vr3 vr2 vr1 vr0 volume (db) 000000 0 000001 0 000010 - 1 000011 - 2 ... ... ... ... ... ... ... 111000 - 55 111001 - 111010 - 111011 - 111100 - 111101 - 111110 - 111111 - vr5 vr4 vr3 vr2 vr1 vr0 volume (db) 000000 0 000001 0 000010 - 1 000011 - 2 ... ... ... ... ... ... ... 111000 - 55 111001 - 111010 - 111011 - 111100 - 111101 - 111110 - 111111 -
1996 jul 17 10 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 bass boost: a 5-bit value to program the bass boost setting. the used set depends on the mode bits. table 13 bass boost settings bb4 bb3 bb2 bb1 bb0 bass boost flat set (db) min set (db) max set (db) 00000 0 0 0 00001 0 0 0 00010 0 2 2 00011 0 4 4 00100 0 6 6 00101 0 8 8 00111 0 10 10 00110 0 12 12 01001 0 14 14 01000 0 16 16 01011 0 18 18 01010 0 18 20 01101 0 18 22 01100 0 18 24 01111 0 18 24 01110 0 18 24 10000 0 18 24 10001 0 18 24 10010 0 18 24 10011 0 18 24 10100 0 18 24 10101 0 18 24 10111 0 18 24 10110 0 18 24 11001 0 18 24 11000 0 18 24 11011 0 18 24 11010 0 18 24 ::::: : : : 11110 0 18 24
1996 jul 17 11 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 treble: a 5-bit value to program the treble setting. the used set depends on the mode bits. table 14 treble settings tr4 tr3 tr2 tr1 tr0 treble flat set (db) min set (db) max set (db) 00000 0 0 0 00001 0 0 0 00010 0 2 2 00011 0 2 2 00100 0 4 4 00101 0 4 4 00111 0 6 6 00110 0 6 6 01001 0 6 6 01000 0 6 6 01011 0 6 6 01010 0 6 6 01101 0 6 6 01100 0 6 6 01111 0 6 6 01110 0 6 6 ::::: : : : 11110 0 6 6 flat/min/max setting selection in the TDA1388 has three setting for the digital sound features bass boost and treble. the possible settings are called flat, min and max. the flat setting has no influence on the audio signal, the minimum setting has a small influence on the audio signal and the maximum setting has a large influence on the audio signal. in the static-pin mode, the flat setting is used for the bass boost and treble filters. in the microcontroller mode, all three settings can by controlled by a register. channel manipulation modes in the TDA1388 there is a channel manipulation function implemented. this function has a fixed value in the static-pin mode, the left signal on the left channel and the right signal on the right channel. in the microcontroller mode several option are possible. the different modes are as follows: normal stereo output left/right reverse output mono left/right output: 1 2 (l+r) output muting with soft mute. de-emphasis de-emphasis is controlled by an external pin in the static-pin mode and by a register in the microcontroller mode.the digital de-emphasis filter is dimensioned to produce the de-emphasis frequency characteristics for the sample rate 44.1 khz. with its 18-bit dynamic range, the digital de-emphasis filter of the TDA1388 is a convenient and component saving alternative to analog de-emphasis. de-emphasis is synchronized to the sample clock, so that operation always takes place on complete samples.
1996 jul 17 12 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 volume control the volume of the left and right channels are controlled by a fixed value (0 db) in the static-pin mode and by separate registers in the microcontroller mode. in the microcontroller mode the values of both channels can vary, independent of each other, from 0 db to - db. since there is no headroom included into the sound control section, the volume control precedes the sound control. full volume and neutral setting (flat) of the sound control results in full-scale output. any tone boost will directly cause clipping, which can be avoided by reduction of the volume setting. bass boost a strong bass boost effect, which is useful in compensating for poor response of portable headphone sets, is implemented digitally in the TDA1388 and can be controlled in the microcontroller mode. in the static-pin mode, the flat setting is fixed. in the microcontroller mode, valid settings range from flat (no influence on audio) to +18 db with step sizes of 2 db in minimum and to +24 db with step sizes of 2 db in maximum. the programmable bass boost filter is a 2nd-order shelving type with a fixed corner frequency of 130 hz for the minimum setting and a fixed corner frequency of 230 hz for the maximum setting and has a butterworth characteristic. because of the exceptional amount of programmable gain, bass boost should be used with adequate prior attenuation, using the volume control. treble a treble effect is implemented digitally in the TDA1388 and can be controlled in the microcontroller mode. in the static-pin mode, the flat setting is fixed. in the microcontroller mode, valid settings range from flat (no influence on audio) to +6 db with step sizes of 2 db in minimum and to +6 db with step sizes of 2 db in maximum. the programmable treble filter is a 1st-order shelving type with a fixed corner frequency of 2.8 khz for the minimum setting and a fixed corner frequency of 5.0 khz for the maximum setting. because of the exceptional amount of programmable gain, treble should be used with adequate prior attenuation, using the volume control. soft mute soft mute is controlled by external pins, for each channel one, in the static-pin mode and by the channel manipulation modes of left or right in the microcontroller mode. when the mute is active for a channel, the value of the sample is decreased smoothly to zero following a raised cosine curve. 32 coefficients are used to step down the value of the data, each one being used 32 times before stepping on to the next. this amounts to a mute transition of 23 ms at f s = 44.1 khz. when the mute is released, the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in the reverse order. the mute, on the left or right channel, is synchronized to the sample clock, so that operation always takes place on complete samples. oversampling and noise shaper the digital filter is four times oversampling filter. it consists of two sections which each increase the sample rate by 2. the 2nd-order noise shaper operates at 64f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique used in combination with a sign-magnitude coding enables high signal-to-noise ratios to be achieved. the noise shaper outputs a 5-bit pdm bitstream signal to the dac. continuous calibration dac the dual 5-bit dac uses the continuous calibration technique. this method, based on charge storage, involves exact duplication of a single reference current source. in the TDA1388, 32 such current sources plus 1 spare source are continuously calibrated. the spare source is included to allow continuous convertor operation. the dac receives a 5-bit data bitstream from the noise shaper. this data is converted so that no current is switched to the output during digital silence (input 00000h). in this way very high signal-to-noise performance is achieved. stereo line driver high precision, low-noise amplifiers together with the internal conversion resistor r conv1 and r conv2 convert the converter output current to a voltage capable of driving a headphone. the voltage is available at v ol and v or (pins 4 and 25). stereo headphone driver high precision, low-noise amplifiers are capable of driving a headphone load. the voltage is available at hpoutl and hpoutr (pins 2 and 27).
1996 jul 17 13 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 handbook, full pagewidth lsb-justified format 16 bits lsb-justified format 18 bits lsb-justified format 20 bits input format i 2 s-bus ws left left left left right right right right 3 2 2 2 15 16 17 18 1 15 16 1 1 3 2 1 msb b2 msb lsb lsb msb b2 msb lsb b2 msb b2 b3 b4 b15 lsb b17 2 15 16 17 18 1 msb b2 b3 b4 lsb b17 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 mgd019 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 2 15 16 1 msb lsb b2 b15 >=8 >=8 bck data ws bck data ws bck data ws bck data fig.3 input formats.
1996 jul 17 14 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 fig.4 timing address mode. handbook, full pagewidth t h;ma t s;ma t h;dat t s;dat t cy bit 0 l3mode l3clk l3data bit 7 mgd016 t lc t hc t s;ma t h;ma fig.5 timing for data transfer mode. handbook, full pagewidth t halt t s;mt t en;dat t h;dat t s;dat t h;dat t 3;dat t halt t h;mt mgd017 t cy bit 0 l3mode l3clk l3data write bit 7 t lc t hc
1996 jul 17 15 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 limiting values in accordance with the absolute maximum rating system (iec 134). all voltages referenced to ground, v ddd =v dda =v ddo = 5 v; t amb =25 c, unless otherwise specified. notes 1. all v dd and v ss connections must be made to the same power supply. 2. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor. 3. equivalent to discharging a 200 pf capacitor via a 2.5 m h series inductor. symbol parameter conditions min. max. unit v dd supply voltage note 1 - 7.0 v t xtal(max) maximum crystal temperature - 150 c t stg storage temperature - 65 +125 c t amb operating ambient temperature - 20 +70 c v es electrostatic handling note 2 - 3000 +3000 v note 3 - 300 +300 v fig.6 multibyte transfer. handbook, full pagewidth t halt address l3data l3clk l3mode address data byte #1 data byte #2 mgd018
1996 jul 17 16 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 thermal characteristics dc characteristics v ddd =v dda =v ddo =5v; t amb =25 c; r l =5k w ; all voltages referenced to ground (pins 1, 13, 21 and 23); unless otherwise speci?ed . notes 1. all power supply pins (v dd and v ss ) must be connected to the same external power supply unit. 2. no operational amplifier load resistor. 3. load capacitance larger than 50 pf, a 22 m h inductor in parallel with a 270 w resistor must be inserted between the load and the operational amplifier output (line output only). symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air sop28 60 k/w ssop28 80 k/w symbol parameter conditions min. typ. max. unit v ddd digital supply voltage note 1 4.5 5.0 5.5 v v dda analog supply voltage note 1 4.5 5.0 5.5 v v ddo operational ampli?er supply voltage note 1 4.5 5.0 5.5 v i ddd digital supply current at digital silence - 7.0 - ma i dda analog supply current at digital silence - 5.0 - ma i ddo operational ampli?er supply current at digital silence - 10 - ma p tot total power dissipation note 2 - 110 - mw digital input pins v ih high level input voltage 0.7v ddd - v ddd + 0.5 v v il low level input voltage -- 0.3v ddd v | i li | input leakage current -- 10 m a c in input capacitance -- 10 pf analog audio pins v ref reference voltage with respect to v ssa 0.45v dda 0.5v dda 0.55v dda v r out(ref) output reference resistance - 3 - k w r conv current-to-voltage conversion resistor - 2.7 - k w i o(max) maximum output current (thd+n)/s < 0.1% r l =32 w - 88 - ma (thd+n)/s < 0.1% r l =16 w - 44 - ma c l output load capacitance note 3 -- 50 pf
1996 jul 17 17 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 ac characteristics (analog) v ddd =v dda =v ddo =5v; f i = 1 khz; t amb =25 c; r l =5k w all voltages referenced to ground (pins 1, 13, 21 and 23); unless otherwise speci?ed . notes 1. proportional to v dda . 2. one output digital silence, the other maximum volume. symbol parameter conditions min. typ. max. unit res resolution -- 18 bits v fs(rms) output voltage swing (rms value) note 1 0.9 1.0 1.1 v v dc(os) output voltage dc offset with respect to reference voltage level v ref - 20 - mv svrr supply voltage ripple rejection v dda and v ddo f ripple = 1 khz; v ripple(p-p) = 100 mv; c pin =10 m f - 40 - db ?d v o ? unbalance between the 2 dac voltage outputs maximum volume - 0.1 - db a ct crosstalk between the 2 dac voltage outputs for line outputs r l =5k w , note 2 - 90 - db crosstalk between the 2 dac voltage outputs for headphone outputs r l =16 w , note 2 - 60 - db r l =32 w , note 2 - 65 - db (thd+n)/s total harmonic distortion plus noise as a function of signal for the line output 0 db signal; r l =5k w -- 85 - 80 db - 0.006 0.013 % - 60 db signal; r l =5k w -- 35 - 30 dba - 1.8 3.2 % total harmonic distortion plus noise as a function of signal for the headphone output 0 db signal; r l =16 w -- 65 - db - 0.056 - % 0 db signal; r l =32 w -- 70 - db - 0.032 - % - 60 db signal; r l =16 w or r l =32 w -- 35 - 30 dba - 1.8 3.2 % s/n signal-to-noise ratio at bipolar zero a weighting; at code 00000h 90 95 - dba
1996 jul 17 18 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 ac characteristics (digital) v ddd =v dda =v ddo = 4.5 to 5.5 v; t amb = - 20 to +70 c; r l =5k w ; all voltages referenced to ground (pins 1, 13, 21 and 23); unless otherwise speci?ed . symbol parameter conditions min. typ. max unit t cy clock cycle f sys = 256f s 81.3 88.6 122 ns f sys = 384f s 54.2 59.1 81.3 ns t cwl f sys low level pulse width 22 -- ns t cwh f sys high level pulse width 22 -- ns serial input data timing (see fig.7) br clock input = data input rate f sys = 256f s - 64f s - f sys = 384f s - 48f s - f sys system clock frequency 8.192 - 18.432 mhz f ws word selection input frequency - 44.1 48 khz t r rise time -- 20 ns t f fall time -- 20 ns t bck(h) bit clock high time 55 -- ns t bck(l) bit clock low time 55 -- ns t s;dat data set-up time 10 -- ns t h;dat data hold time 20 -- ns t s;ws word selection set-up time 20 -- ns t h;ws word selection hold time 10 -- ns fig.7 timing and input signals. handbook, full pagewidth mgd567 ws bck data right lsb msb left t s;ws t h;ws t s;dat t h;dat t bck(h) t bck(l) t cy t r t r
1996 jul 17 19 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 test and application information fig.8 application diagram. (1) optional. (2) chip inductor blm32a07. handbook, full pagewidth v ref appl0/da appl1/mo tc acp appl2/cl data ws bck 19 14 sysclk syssel 15 7 if1 if2 8 13 v ssd v ddd 12 5 TDA1388 4 23 18 11 10 9 16 17 22 3 28 1 6 2 27 24 r l 25 26 v sso1 v ssa v ddo v dda 100 w 100 m f 10 m f 100 nf 100 nf 330 m f 100 nf 100 nf 100 nf filtcl hpinl hpoutr hpoutl v ol 1 nf 100 m f 4.7 w 4.7 w + 5 v i 2 s-bus or lsb-justified serial input data system clock input l3 (1) (2) (1) from microcontroller 20 21 47 m f 4.7 m f 330 m f 330 m f r1 10 k w mgd152 100 w filtcr hpinr v or v sso2 1 nf 47 m f 4.7 m f r1 10 k w
1996 jul 17 20 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 package outlines unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot136-1 91-08-13 95-01-24 x 14 28 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a e 15 1 (a ) 3 a y 0.25 075e06 ms-013ae pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.71 0.69 0.30 0.29 0.050 1.4 0.055 0.42 0.39 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale so28: plastic small outline package; 28 leads; body width 7.5 mm sot136-1
1996 jul 17 21 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150ah 93-09-08 95-02-04 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2.0
1996 jul 17 22 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all so and ssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering so wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. ssop wave soldering is not recommended for ssop packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions, only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1) . m ethod (so and ssop) during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 jul 17 23 philips semiconductors objective speci?cation bitstream continuous calibration ?lter-dac for cd-rom audio applications TDA1388 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
internet: http://www.semiconductors.philips.com/ps/ (1) TDA1388_2 june 26, 1996 11:51 am philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca50 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 83749, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 926 5361, fax. +7 095 564 8323 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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